Gate driver circuits including amorphous silicon transistors (also referred to as a-Si TFTs) have been developed (see Patent Documents 1 and 2, for example). Such a gate driver includes a transistor for controlling the timing of outputting a high voltage to a gate line (such a transistor is also referred to as a pull up transistor). The pull up transistor has a source and a drain one of which is connected to a clock line and the other of which is connected to a gate line. In addition, such a gate driver employs a driving method in which the potential of a gate of the pull up transistor is made higher than the high (H-level) potential of a clock signal by capacitive coupling. In order to achieve this driving method, it is necessary to make the gate of the pull up transistor be floating. It is therefore necessary to turn off all the transistors that are connected to the gate of the pull up transistor.